1. Technical Field
The present invention relates to a technique for detecting phases of multiphase clocks and, more particularly, to a technique for detecting a phase error in multiphase clocks used in a semiconductor integrated circuit.
2. Related Art
There is a case that multiphase clocks are used for, for example, high-speed parallel arithmetic operation as operation clocks of a semiconductor integrated circuit (hereinafter referred to as the “integrated circuit”) such as an LSI. The multiphase clocks are a group of clock signals having the same cycle and different phases. Typically, N-phase clocks (N is an integer of 2 or larger) is clock signals of the zero-th phase to the (N−1)-th phase having the same cycle. The clock signal of the k-th phase (k is any of zero to N−1) is a signal delayed from the clock signal of the zero-th phase by (T/N)·k (where T=1 cycle). As disclosed in Japanese Unexamined Patent Publication No. 2001-350539, multiphase clocks can be generated by using a PLL (Phase-Locked Loop) circuit.
The phases of the multiphase clocks may be deviated due to variations in the interconnection width and thickness in an integrated circuit or due to ambient environment such as temperature. For example, in the N-th phase clock, the phase difference between the clock signals having the k-th and (k+1)-th phases has to be maintained to 2n/N. When multiphase clocks are transmitted in the integrated circuit, there is the case where the phase difference becomes not equal to 2n/N and a phase error occurs.
For example, a technique of correcting a phase shift of a clock signal is disclosed in Japanese Patent Application Publication Nos. 2006-186660, H05-191237, and 2000-077990.
Conventionally, a test on the phase states of multiphase clocks in an integrated circuit is conducted by transferring multiphase clocks from an output buffer built in the integrated circuit to an external measuring device (for example, an oscilloscope) and measuring the pulse waveforms of the transferred multiphase clocks by the external measuring device. In such measurement, a phase error occurring when the multiphase clocks are distributed in the integrated circuit is detected, and a detection result can be reflected in product development. However, to test the phase states of the multiphase clocks of high frequencies, an output buffer of high efficiency which can operate at high speed has to be assembled in an integrated circuit. It causes a problem that the design cost of the integrated circuit and the circuit scale increase.